1. Field of the Invention
The present invention relates to an A/D converter (analog-to-digital converter), and particularly to a pipelined A/D converter, in which signals are sent downstream in a pipeline fashion, and A/D conversion is effected on the signals in each stage,
2. Description of the Background Art
An A/D converter is a circuit for discretizing or digitizing an analog signal, of which voltage continuously changes with time, in a time axis direction and a voltage axis direction, and thereby converting it to a binary digital signal. Such A/D converters have been widely used as interfaces in various devices.
Various manners have been proposed for discretizing the voltage of the analog signal in view of precision and conversion speed of the A/D converters. One of the known manners is executed by a pipelined A/D converter, which sends the signal downstream in a pipeline fashion, and performs A/D conversion in each stage.
FIG. 14 is a block diagram schematically showing a whole structure of a conventional pipelined A/D converter.
Referring to FIG. 14, an A/D converter 100 is formed of stages of (N−1) in number connected in a pipeline fashion, and includes arithmetic circuits 101-103 corresponding to the first to (N−1)th stages, respectively. A/D converter 100 also includes a digital error correction circuit 12, which receives bit data provided from each stage, and performs error correction processing to provide a final digital signal of N bits.
In A/D converter 100, the arithmetic circuit in each stage other than an arithmetic circuit 103 in the final stage basically performs one-bit conversion. However, redundancy of 0.5 bits is employed for providing data of 1.5 bits (ternary data) to digital error correction circuit 12. Arithmetic circuit 103 in the final stage converts the analog signal received from the preceding stage to 2-bit data, and provides it to digital error correction circuit 12.
Digital error correction circuit 12 receives the bit data provided from each stage, performs addition of the respective bit data and error processing, and finally outputs the N-bit digital signal.
In A/D converter 100, when an arithmetic circuit 101 forming a first stage receives an analog input signal Vin, arithmetic circuit 101 converts analog input signal Vin to 1.5-bit data, and provides the converted bit data to digital error correction circuit 12. Arithmetic circuit 101 doubles a residual between analog input signal Vin and a voltage corresponding to the converted bit data, and provides a doubled residual voltage Vres1 to the second stage.
When an arithmetic circuit 102 forming a second stage receives residual voltage Vres1, arithmetic circuit 102 converts it to 1.5-bit data, and provides the converted bit data to digital error correction circuit 12. Arithmetic circuit 102 doubles a residual between residual voltage Vres1 and a voltage corresponding to the converted bit data, and provides a doubled residual voltage Vres2 to a next stage.
Thereafter, the A/D conversion is performed similarly in each stage, and arithmetic circuit 103 forming the final (N−1)th stage receives a residual voltage Vres(N−2) from a preceding stage. Thereby, arithmetic circuit 103 converts residual voltage Vres(N−2) to 2-bit data, and provides the converted bit data to digital error correction circuit 12.
Based on the bit data provided from each stage, digital error correction circuit 12 performs addition of the respective data as well as the error correction, and finally provides an N-bit digital signal.
FIG. 15 is a function block diagram illustrating a structure and a function of the arithmetic circuit shown in FIG. 14. All the foregoing arithmetic circuits have the same structure, and FIG. 15 representatively shows a structure of arithmetic circuit 102. Arithmetic circuit 103 in the final stage provides the output data of 2 bits instead of the 1.5-bit output data shown in FIG. 15.
Referring to FIG. 15, arithmetic circuit 102 includes a sample hold portion 121, a subtracting portion 122, an amplifying portion 123, an A/D sub-converter 24 and a D/A sub-converter (digital-to-analog sub-converter) 25.
Sample hold portion 121 samples residual voltage Vres1 provided from arithmetic circuit 101 in the preceding stage, and holds the voltage thereof. A/D sub-converter 24 converts the residual voltage Vres1 to 1.5-bit data, and provides the converted bit data to digital error correction circuit 12 (not shown in FIG. 15).
D/A sub-converter 25 converts the data, which is converted into the digital data by A/D sub-converter 24, to an analog voltage Vr2. Subtracting portion 122 subtracts analog voltage Vr2, which is provided by D/A sub-converter 25, from voltage Vres1 held by sample hold portion 121.
Amplifying portion 123 amplifies the voltage provided from subtracting portion 122 by an amplification factor of 2, and provides the amplified voltage to a next stage as residual voltage Vres2 in the second stage.
In this manner, the voltage width of the input range of each stage can be equal to those of the other stages.
FIG. 16 is a circuit diagram showing a structure of a major portion of arithmetic circuit 102 shown in FIG. 12. FIG. 16 shows specific circuit structures of sample hold portion 121, subtracting portion 122 and amplifying portion 123 shown in FIG. 15. Although not shown in FIGS. 14 and 15, the above A/D converter practically has a circuit structure of a differential type. More specifically, analog input voltage Vin is formed of a signal VinA and a signal VinB produced by inverting signal VinA with respect to a common voltage Vcom. Residual voltage Vresi (i is a natural number from 1 to (N−2)) is formed of a voltage VresiA and a voltage VresiB produced by inverting voltage VresiA with respect to common voltage Vcom. Analog voltage Vri converted by D/A sub-converter 25 is formed of a voltage VriA and a voltage VriB produced by inverting voltage VriA with respect to common voltage Vcom.
Referring to FIG. 16, arithmetic circuit 102 includes switches S101-S108, capacitors C101-C104, differential amplifier 137, nodes ND101-ND106, input nodes 131-134 and output nodes 135 and 136.
Input nodes 132 and 133 receive residual voltages Vres1A and Vres1B provided from the preceding stages, respectively. Input nodes 131 and 134 receive analog voltages Vr2A and Vr2B provided from D/A sub-converter 25. Switch S101 is connected between input node 131 and node ND101, and switch S102 is connected between input node 132 and node ND101. Switch S103 is connected between input node 133 and node ND102, and switch S104 is connected between input node 134 and node ND102.
Switch S105 is connected between output node 135 and node ND103, and switch S106 is connected between nodes ND101 and ND103. Switch S107 is connected between nodes ND102 and ND104, and switch S108 is connected between output node 136 and node ND104.
Capacitor C101 is connected between nodes ND103 and ND105, and capacitor C102 is connected between nodes ND101 and ND105. Capacitor C103 is connected between nodes ND102 and ND106, and capacitor C104 is connected between nodes ND104 and ND106.
Differential amplifier 137 has input terminals connected to nodes ND105 and ND106, respectively, and also has output terminals connected to output nodes 135 and 136, respectively. Differential amplifier 137 amplifies a voltage difference between nodes ND105 and ND106, and provides it to output nodes 135 and 136.
Arithmetic circuit 102 has two operation modes, i.e., a “sample mode” and a “hold mode”. FIG. 16 shows a state in a sample mode. In the sample mode, switches S102, S103, S106 and S107 are turned on, and the other switches are turned off. Therefore, capacitors C101 and C102 sample residual voltage Vres1A, and capacitors C103 and C104 sample residual voltage Vres1B.
FIG. 17 shows a state of arithmetic circuit 102 shown in FIG. 15 and operating in the hold mode.
In the hold mode, as shown in FIG. 17, switches S101, S104, S105 and S108 are turned on, and the other switches are turned off. Thereby, capacitors C101 and C104 operate as feedback capacitors. Thereby, output node 135 is supplied with a voltage produced by subtracting analog voltage Vr2A from residual voltage Vres1A held in each of capacitors C101 and C102, and output node 136 is supplied with a voltage produced by subtracting analog voltage Vr2B from residual voltage Vres1B held in each of capacitors C103 and C104. More specifically, residual voltages Vres2A and Vres2B provided to output nodes 135 and 136 can be expressed by the following formulas, respectively, in which capacitances are represented by the same reference characters as the corresponding capacitors, respectively.Vres2A=(1+C102/C101)Vres1A−(C102/C101)Vr2A  (1)Vres2B=(1+C103/C104)Vres1B−(C103/C104)Vr2B  (2)
According to the above formulas, if capacitances C101 and C102 have accurately the same magnitude, or if the capacitors C103 and C104 have accurately the same magnitude, an input voltage, i.e., residual voltage Vres1A or Vres1B is accurately doubled.
In practice, however, variations are present in magnitude or capacitance of the capacitors. Therefore, residual voltages Vres1A and Vres1B are not accurately doubled, and an error caused thereby affects the downstream stages to deteriorate precision of the A/D converter. More specifically, if an A/D converter of, e.g., 14 bits multiplies the input voltage by a factor of 1.999 in each stage due to variations in capacitors, a voltage multiplied by a factor of only 1.99912 (=4071.5) is practically input to the final stage although a voltage multiplied by a factor of 212 (=4096) is to be ideally input thereto.
One of manners, which can overcome the above problem relating to deterioration of accuracy due to variations in capacitors, is disclosed by Hsin-Shu Chen, et al., “A 14-b 20-MSamples/s CMOS Pipelined ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 36, No. 6, pp. 997-1001, June, 2001.
An A/D converter employing the manner disclosed therein may also be referred as an “averaging A/D converter” hereinafter. A general structure of the averaging A/D converter is the same as that shown in FIG. 14, but differs from A/D converter 100 in structures of the arithmetic circuits in the respective stages.
FIG. 18 is a function block diagram illustrating a structure and a function of an arithmetic circuit in the averaging A/D converter. All the arithmetic circuits have the same structure. FIG. 18 representatively shows a structure of an arithmetic circuit 102A corresponding to a second stage. In a final stage, the arithmetic circuit provides 2-bit output data instead of 1.5-bit output data shown in FIG. 18.
Referring to FIG. 18, arithmetic circuit 102A includes a sample hold portion 141, a subtracting portion 142, an amplifying portion 143, an averaging portion 144, A/D sub-converter 24 and D/A sub-converter 25.
Sample hold portion 141 samples residual voltage Vres1 provided from the arithmetic circuit in the preceding stage, and holds the voltage. A/D sub-converter 24 and D/A sub-converter 25 are the same as those already described with reference to FIG. 15. Subtracting portion 142 subtracts analog voltage Vr2 converted by D/A sub-converter 25 from voltage Vres1 held by sample hold portion 141.
Amplifying portion 143 amplifies the voltage provided from subtracting portion 142 by an amplification factor of 2. The averaging A/D converter has three operation modes, i.e., “sample mode”, “hold mode” and “averaging mode”. In the hold mode, amplifying portion 143 amplifies the voltage provided from subtracting portion 142 by an amplification factor of 2, and averaging portion 144 samples a voltage Vout1 provided from amplifying portion 143.
In the subsequent averaging mode, amplifying portion 143 amplifies a voltage, which is arithmetically operated after interchanging the capacitors as will be described later with reference to a circuit diagram, by an amplification factor of 2, and averaging portion 144 averages an output voltage Vout2 provided from amplifying portion 143 and voltage Vout1 sampled in the hold mode. Averaging portion 144 provides the voltage thus averaged to the next stage as residual voltage Vres2 of the second stage.
FIG. 19 is a circuit diagram showing a structure of a major portion of arithmetic circuit 102A shown in FIG. 18. FIG. 19 shows specific circuit structures of sample hold portion 141, subtracting portion 142, amplifying portion 143 and averaging portion 144 shown in FIG. 18. In practice, this averaging A/D converter has a circuit structure of a differential type, similarly to conventional A/D converter 100 already described.
Referring to FIG. 19, arithmetic circuit 102A includes an amplifier circuit 102A.1 and an averaging circuit 102A.2. Amplifier circuit 102A.1 includes a structure, which is the same as that of arithmetic circuit 102 in conventional A/D converter 100 shown in FIG. 16, and further includes switches S111-S115 and nodes ND111-ND114. Averaging circuit 102A.2 includes switches S121-S125, capacitors C121-C124, a differential amplifier 138, nodes ND121-ND124 and output nodes 135 and 136.
Switch S111 is connected between nodes ND113 and ND111. Switch S112 is connected between nodes ND101 and ND111. Switch S113 is connected between nodes ND102 and ND112, and switch S114 is connected between nodes ND114 and ND112. Switch S115 is connected between nodes ND113 and ND114.
Switch S121 is connected between output node 135 and node ND121, and switch S122 is connected between nodes ND113 and ND121. Switch S123 is connected between nodes ND114 and ND122, and switch S124 is connected between output node 136 and node ND122. Switch S125 is connected between output nodes 135 and 136.
Capacitor C121 is connected between nodes ND121 and ND123, and capacitor C122 is connected between nodes ND114 and ND123, Capacitor C123 is connected between nodes ND113 and ND124, and capacitor C124 is connected between nodes ND122 and ND124.
Differential amplifier 138 has input terminals connected to nodes ND123 and ND124, respectively, and have output terminals connected to output nodes 135 and 136, respectively. Differential amplifier 138 amplifies the voltage difference between nodes ND123 and ND124, and provides it to output nodes 135 and 136.
As described above, arithmetic circuit 102A has three operation modes, i.e., “sample mode”, “hold mode” and “averaging mode”. FIG. 19 shows a state in the sample mode. In the sample mode, switches S102, S103, S106, S112, S113, S107 and S115 are turned on, and the other switches are turned off. Therefore, capacitors C101 and C102 sample residual voltage Vres1A, and capacitors C103 and C104 sample residual voltage Vres1B.
FIG. 20 shows a state in the hold mode of arithmetic circuit 102A shown in FIG. 18.
In the hold mode shown in FIG. 20, amplifier circuit 102A.1 enters the following state. Switches S101, S104, S105, S112, S113 and S108 are turned on, and the other switches are turned off. Thereby, capacitors C101 and C104 operate as feedback capacitors, and capacitors C102 and C103 operate as capacitors sampling analog voltages Vr2A and Vr2B, respectively.
Node ND113 is supplied with a voltage produced by subtracting analog voltage Vr2A sampled by capacitor C102 from residual voltage Vres1A held by each of capacitors C101 and C102, and node ND114 is supplied with a voltage produced by subtracting analog voltage Vr2B sampled by capacitor C103 from residual voltage Vres1B held by each of capacitors C103 and C104. More specifically, voltages Vout1A and Vout1B provided to nodes ND113 and ND114 in the hold mode can be expressed by the following formulas, respectively, in which capacitances are represented by the same reference characters as the corresponding capacitors, respectively.Vout1A=(1+C102/C101)Vres1A−(C102/C101)Vr2A  (3)Vout1B=(1+C103/C104)Vres1B−(C103/C104)Vr2B  (4)
In averaging circuit 102A.2, switches S122 and S123 are turned on, and switches S121 and S124 are turned off. Thereby, capacitors C121 and C123 sample voltage Vout1A provided from amplifier circuit 102A.1 in the hold mode, and capacitors C122 and C124 sample voltage Vout1B.
FIG. 21 shows a state in the averaging mode of arithmetic circuit 102A shown in FIG. 18.
In the averaging mode shown in FIG. 21, amplifier circuit 102A.1 enters the following state. Switches S101, S104, S106, S111, S114 and S107 are turned on, and the other switches are turned off. Thereby, capacitors C102 and C103 operate as feedback capacitors, and capacitors C101 and C104 operate as capacitors sampling analog voltages Vr2A and Vr2B, respectively. Thus, in the averaging mode, the capacitors in amplifier circuit 102A.1 are interchanged with respect to those in the hold mode.
Node ND113 is supplied with a voltage produced by subtracting analog voltage Vr2A sampled by capacitor C101 from residual voltage Vres1A held by each of capacitors C101 and C102, and node ND114 is supplied with a voltage produced by subtracting analog voltage Vr2B sampled by capacitor C104 from residual voltage Vres1B held by each of capacitors C103 and C104. More specifically, voltages Vout2A and Vout2B provided to nodes ND113 and ND114 in the averaging mode can be expressed by the following formulas, respectively.Vout2A=(1+C101/C102)Vres1A−(C101/C102)Vr2A  (5)Vout2B=(1+C104/C103)Vres1B−(C104/C103)Vr2B  (6)
In averaging circuit 102A.2, switches S121 and S124 are turned on, and switches S122 and S123 are turned off. Thereby, voltages Vout1A and Vout1B sampled in the hold mode and voltages Vout2A and Vout2B provided from amplifier circuit 102A.1 in the averaging mode are averaged. More specifically, residual voltages Vres2A and Vres2B provided to output nodes 135 and 136 can be expressed by the following formulas, respectively.                     Vres2A        =                                            (                              1                /                2                            )                        ⁢                          {                                                (                                      1                    +                                          C102                      /                      C101                                                        )                                +                                  (                                      1                    +                                          C101                      /                      C102                                                        )                                            }                        ⁢            Vres1A                    -                                    (                              1                /                2                            )                        ⁢                          (                                                C102                  /                  C101                                +                                  C101                  /                  C102                                            )                        ⁢                                                   ⁢            Vr2A                                              (        7        )                                Vres2B        =                                            (                              1                /                2                            )                        ⁢                          {                                                (                                      1                    +                                          C103                      /                      C104                                                        )                                +                                  (                                      1                    +                                          C104                      /                      C103                                                        )                                            }                        ⁢            Vres1B                    -                                    (                              1                /                2                            )                        ⁢                          (                                                C103                  /                  C104                                +                                  C104                  /                  C103                                            )                        ⁢            Vr2B                                              (        8        )            
Assuming that there is a relationship of (C101=C104=C and C102=C103=C(1+α)), where α represent variations in capacitor), the formulas (7) and (8) can be expressed by the following formulas because α is usually of a small value:Vres2A=2Vres1A−Vr2A  (9)Vres2B=2Vres1B−Vr2B  (10)
α does not appear in the above formulas so that the averaging A/D converter can remove an influence by variations in capacitors.
As described above, variations in capacitors impair the conversion precision in the conventional A/D converter. However, the averaging A/D converter can remove the influence, which may be exerted by the variations in capacitors, and thus can achieve precise conversion.
However, the averaging A/D converter includes amplifier circuit 102A.1 and averaging circuit 102A.2 as shown in FIGS. 19 to 21, and therefore requires a large circuit area. Also, differential amplifier 138 in averaging circuit 102A.2 increases noises. Further, the capacitors must have large sizes for allowing an influence by noises, resulting in further increase in circuit area and increase in power consumption.
In recent years, it has been increasingly required in electronic devices to reduce power consumption for reduction in size and improvement of portability, in addition to requirement for improvement of functions, and therefore it has been severely required in the A/D converters employed in such electronic devices to reduce sizes and power consumption. Although the averaging A/D converter already described can eliminate the influence by variations in capacitors, and thus is useful in improvement of precision (and functions), it cannot achieve the required reduction in size and power consumption.